1. Technical Field
The present disclosure generally relates to advanced transistor structures for use in analog integrated circuits.
2. Description of the Related Art
Advanced integrated circuits typically feature strained channel devices, silicon-on-insulator (SOI) substrates, FinFET structures, or combinations thereof, in order to continue scaling transistor gate lengths below 20 nm. Such technologies allow the channel length of the transistor to be made smaller while minimizing detrimental consequences such as current leakage and other short channel effects.
A FinFET is an electronic switching device that features a conduction channel in the form of a semiconducting fin that extends outward from the substrate surface. In such a device, the gate, which controls current flow in the fin, wraps around three sides of the fin so as to influence current flow from three surfaces instead of one. The improved control achieved with a FinFET design results in faster switching performance in the “on” state and less current leakage in the “off” state than is possible in a conventional planar device.
Incorporating strain into the channel of a semiconductor device stretches the crystal lattice, thereby increasing charge carrier mobility in the channel so that the device becomes a more responsive switch. Introducing compressive strain into a PFET transistor tends to increase hole mobility in the channel, resulting in a faster switching response to changes in voltage applied to the transistor gate. Likewise, introducing a tensile strain into an NFET transistor tends to increase electron mobility in the channel, also resulting in a faster switching response.
There are many ways to introduce strain into the channel region of a FinFET. Techniques for introducing strain typically entail incorporating into the device epitaxial layers of one or more materials having crystal lattice dimensions or geometries that differ slightly from those of the silicon substrate. The epitaxial layers can be made of doped silicon or silicon germanium (SiGe), for example. Such epitaxial layers can be incorporated into source and drain regions, or into the transistor gate that is used to modulate current flow in the channel, or into the channel itself, which is the fin. Alternatively, strain can be induced in the fin from below the device by using various types of SOI substrates. An SOI substrate features a buried insulator, typically a buried oxide layer (BOX) underneath the active area. SOI FinFET devices have been disclosed in patent applications assigned to the present assignee, for example, U.S. patent application Ser. No. 14/231,466, entitled “SOI FinFET Transistor with Strained Channel,” U.S. patent application Ser. No. 14/588,116, entitled “Silicon Germanium-on-insulator FinFET,” and U.S. patent application Ser. No. 14/588,221, entitled “Defect-Free Strain-Relaxed Buffer Layer,” all of which are hereby incorporated by reference in their entireties.
Short channel transistors in which the source and drain regions are very close together permit high speed switching, but they are generally less reliable and offer less precise control than long channel devices. Generally, it is desirable to have both short channel and long channel devices available on the same chip, e.g., as discussed in U.S. Pat. No. 7,723,192 to Carter et al. While it is relatively straightforward to include both types of devices in a digital integrated circuit, state-of-the-art analog designs pose a particular challenge. In order to prevent electromagnetic interference among the transistors on an analog chip, it is desirable to maintain some distance between neighboring devices. This limits the ability of circuit designers to shrink analog designs with each new technology generation. Prevention of crosstalk is of particular concern in nanoscale technologies, for which typical short channel lengths are now expected to be as low as about 7 nm.